Re: LTSpice model for a SiC MOSFET

On Tue, 27 May 2025 14:16:11 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:

Bill Sloman <bill.sloman@ieee.org> wrote:
>

On 27/05/2025 9:09 am, john larkin wrote:

>
[...]

The specs, as far as I can tell, suggest 1KV at 1 ma in and 3.3v at 3
ma out. The required efficiency is then 1%.

 
Actually 1kV at 10uA in.

>
Good grief!   A 10-megohm quarter watt resistor with a zener diode is
the obvious answer.
>

A 3.3v zener will probably leak more than 10uA. Low voltage zeners are
awful.

And he wants 3 mA out... I think.

[...]

Misunderstanding the constraints can lead people to propose
inappropriate solutions.

>
How can anyone misunderstand something they have never been told?

Bill was the confused person.

The problem gets much more interesting with 10 uA in and 99%
efficiency requirement.

A Baxandall isn't going pull microamps at 1 KV.