Sujet : Re: Zilog stopping Z80 production
De : blockedofcourse (at) *nospam* foo.invalid (Don Y)
Groupes : sci.electronics.designDate : 24. Apr 2024, 04:00:00
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <v09p38$1uqd3$2@dont-email.me>
References : 1 2
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On 4/23/2024 5:08 PM, Edward Rawde wrote:
It must be trivial to get a VHDL/Verilog model and make your own by now.
The problem with all the early/simple/trivial processors is getting
the rest of the system to run as fast as the core can. E.g., running
a core at ~200MHz and expecting the same bus timing means < 5ns memory.
(for a Z80, that would be ~10ns as the bus timing is inherently slower)
The better option is to embed the core *in* a design to give you
the advantages of a programmable sequencer (instead of "junk logic")
The 6809 was my preference but took a few more years.