Re: LTSpice model for a SiC MOSFET

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Sujet : Re: LTSpice model for a SiC MOSFET
De : bill.sloman (at) *nospam* ieee.org (Bill Sloman)
Groupes : sci.electronics.design
Date : 20. May 2025, 09:36:19
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <100heu6$25c6d$1@dont-email.me>
References : 1 2 3 4 5 6
User-Agent : Mozilla Thunderbird
On 20/05/2025 5:28 am, legg wrote:
On Mon, 19 May 2025 23:12:50 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
 
On 19/05/2025 10:48 pm, legg wrote:
On Mon, 19 May 2025 18:27:01 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>
On 19/05/2025 2:12 am, legg wrote:
On Sun, 18 May 2025 18:11:58 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>
I'm looking at a problem where somebody wants to step down a 1kV low
current source to 3.3V.
>
The Baxandall class-D oscillator could do it, but it needs a pair 1.7kV
MOSFETs for the job. The Infineon SiC IMH170R450M1 would do it - though
it's a much higher current part (10A) than the job needs (about 1mA).
>
I've dived into the Infineon rabbit-hole which promises LTSpice models,
but wasn't able to find one.
>
Does anybody know of a similar - ideally cheaper and smaller - part for
which there is an LTSpice model?
>
1kv, sitting there all alone and bashfull. Not a common occurEnce.
Is this the only power source in the vicinity? Tell us more.
>
It's not my project. I just got asked about what a Baxandall
down-converter for a 1kV 10uA source would look like.
>
Because it's not my project I'm not at liberty to talk about the power
source. My first thought was an intensely radio-active source pushing
out a lot of high energy beta rays (electrons) or alpha rays (helium
nuclei), but it isn't.
>
>
It sort of limits your ability to help.
>
I know what the power source is - in general terms. I haven't got any
kind of okay to talk about it
>
At 1W, you should be able to get away with murder, if efficiency
isn't really an issue.
>
Efficiency is an issue, if only on the sense that a 0.1W power source
isn't up to much, so even 50% efficiency would be nice. Jim Williams got
about 93% out of the Baxandall configuration, but 50% might be good enough.
 1KV 1ma 1W. Anything low powered will have efficiency issues
 At 100mW it's a different animal.
The 1ma referred to the current-carrying constraint on the switching transistor, not the power source. The Baxandall configuration relies on reactive current circulating inside the tank circuit maintain the output voltage, and some of that can flow through the switches.

I was suggesting a repurposed CCFL transformer for use as an
inductor in a buck reg configuration, because they're cheap,
available and wound for high voltage with low distributed
capacitance. The normal drive winding addresses 8-20V bulh
control. Backwards, like I suggested.
Got a part number?

Lowest frequency to deal with other caps in the viscinity, as
the original CCFL will have sensibly done.
Not a good idea. You really want to run a inverter as fast as the core material (and the switches) will allow. This isn't a CCFL application so the stray capacitances are less of a problem.
--
Bill Sloman, Sydney

Date Sujet#  Auteur
18 May 25 * LTSpice model for a SiC MOSFET125Bill Sloman
18 May 25 +* Re: LTSpice model for a SiC MOSFET62john larkin
19 May 25 i`* Re: LTSpice model for a SiC MOSFET61Bill Sloman
19 May 25 i +* Re: LTSpice model for a SiC MOSFET34john larkin
19 May 25 i i`* Re: LTSpice model for a SiC MOSFET33Bill Sloman
19 May 25 i i +* Re: LTSpice model for a SiC MOSFET16john larkin
19 May 25 i i i`* Re: LTSpice model for a SiC MOSFET15Bill Sloman
19 May 25 i i i `* Re: LTSpice model for a SiC MOSFET14Edward Rawde
19 May 25 i i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May 25 i i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i i  `* Re: LTSpice model for a SiC MOSFET11Bill Sloman
20 May 25 i i i   `* Re: LTSpice model for a SiC MOSFET10Mike Perkins
20 May 25 i i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i i i     `* Re: LTSpice model for a SiC MOSFET [OT]8Liz Tuddenham
21 May 25 i i i      `* Re: LTSpice model for a SiC MOSFET [OT]7legg
21 May 25 i i i       +* Re: LTSpice model for a SiC MOSFET [OT]5Liz Tuddenham
21 May 25 i i i       i`* Re: LTSpice model for a SiC MOSFET [OT]4john larkin
21 May 25 i i i       i +* Re: LTSpice model for a SiC MOSFET [OT]2Phil Hobbs
21 May 25 i i i       i i`- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
21 May 25 i i i       i `- Re: LTSpice model for a SiC MOSFET [OT]1Liz Tuddenham
21 May 25 i i i       `- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
19 May 25 i i `* Re: LTSpice model for a SiC MOSFET16Edward Rawde
19 May 25 i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May 25 i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i  `* Re: LTSpice model for a SiC MOSFET13Bill Sloman
20 May 25 i i   `* Re: LTSpice model for a SiC MOSFET12Edward Rawde
20 May 25 i i    +- Re: LTSpice model for a SiC MOSFET1john larkin
20 May 25 i i    +- Re: LTSpice model for a SiC MOSFET1John R Walliker
20 May 25 i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i i     `* Re: LTSpice model for a SiC MOSFET8Edward Rawde
21 May 25 i i      `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May 25 i i       `* Re: LTSpice model for a SiC MOSFET6Edward Rawde
21 May 25 i i        +- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i        `* Re: LTSpice model for a SiC MOSFET4john larkin
21 May 25 i i         +* Re: LTSpice model for a SiC MOSFET2Edward Rawde
21 May 25 i i         i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i         `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May 25 i +* Re: LTSpice model for a SiC MOSFET20legg
19 May 25 i i+* Re: LTSpice model for a SiC MOSFET11Bill Sloman
19 May 25 i ii`* Re: LTSpice model for a SiC MOSFET10legg
20 May 25 i ii `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i ii  `* Re: LTSpice model for a SiC MOSFET8legg
20 May 25 i ii   +* Re: LTSpice model for a SiC MOSFET4john larkin
20 May 25 i ii   i`* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i ii   i `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May 25 i ii   i  `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i ii   `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i ii    `* Re: LTSpice model for a SiC MOSFET2legg
21 May 25 i ii     `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i`* Re: LTSpice model for a SiC MOSFET8john larkin
20 May 25 i i `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
26 May 25 i i  `* Re: LTSpice model for a SiC MOSFET6Cursitor Doom
26 May 25 i i   +* Re: LTSpice model for a SiC MOSFET2john larkin
26 May 25 i i   i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
26 May 25 i i   `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
26 May 25 i i    `* Re: LTSpice model for a SiC MOSFET2Cursitor Doom
27 May 25 i i     `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
25 May 25 i `* Re: LTSpice model for a SiC MOSFET6JM
26 May 25 i  `* Re: LTSpice model for a SiC MOSFET5Bill Sloman
26 May 25 i   `* Re: LTSpice model for a SiC MOSFET4JM
26 May 25 i    `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
27 May 25 i     `* Re: LTSpice model for a SiC MOSFET2JM
28 May 25 i      `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
18 May 25 +- Re: LTSpice model for a SiC MOSFET1legg
18 May 25 +* Re: LTSpice model for a SiC MOSFET6legg
19 May 25 i`* Re: LTSpice model for a SiC MOSFET5Bill Sloman
19 May 25 i `* Re: LTSpice model for a SiC MOSFET4legg
19 May 25 i  `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
19 May 25 i   `* Re: LTSpice model for a SiC MOSFET2legg
20 May 25 i    `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May 25 +* Re: LTSpice model for a SiC MOSFET37Liz Tuddenham
19 May 25 i+* Re: LTSpice model for a SiC MOSFET7john larkin
22 May 25 ii`* Re: LTSpice model for a SiC MOSFET6Liz Tuddenham
22 May 25 ii `* Re: LTSpice model for a SiC MOSFET5john larkin
22 May 25 ii  `* Re: LTSpice model for a SiC MOSFET4Liz Tuddenham
22 May 25 ii   `* Re: LTSpice model for a SiC MOSFET3john larkin
23 May 25 ii    `* Re: LTSpice model for a SiC MOSFET2Liz Tuddenham
23 May 25 ii     `- Re: LTSpice model for a SiC MOSFET1john larkin
20 May 25 i`* Re: LTSpice model for a SiC MOSFET29Bill Sloman
20 May 25 i +* Re: LTSpice model for a SiC MOSFET8Liz Tuddenham
20 May 25 i i`* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May 25 i i `* Re: LTSpice model for a SiC MOSFET6Liz Tuddenham
21 May 25 i i  +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i i  i`* Re: LTSpice model for a SiC MOSFET2Liz Tuddenham
21 May 25 i i  i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i  `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May 25 i i   `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i `* Re: LTSpice model for a SiC MOSFET20KevinJ93
21 May 25 i  `* Re: LTSpice model for a SiC MOSFET19Bill Sloman
22 May 25 i   `* Re: LTSpice model for a SiC MOSFET18KevinJ93
22 May 25 i    +* Re: LTSpice model for a SiC MOSFET8Bill Sloman
22 May 25 i    i`* Re: LTSpice model for a SiC MOSFET7piglet
22 May 25 i    i +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
22 May 25 i    i i`* Re: LTSpice model for a SiC MOSFET2piglet
23 May 25 i    i i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
22 May 25 i    i +* Re: LTSpice model for a SiC MOSFET2john larkin
22 May 25 i    i i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
23 May 25 i    i `- Re: LTSpice model for a SiC MOSFET1legg
27 May 25 i    `* Re: LTSpice model for a SiC MOSFET9john larkin
27 May 25 i     `* Re: LTSpice model for a SiC MOSFET8Bill Sloman
27 May 25 i      `* Re: LTSpice model for a SiC MOSFET7Liz Tuddenham
19 May 25 +* Re: LTSpice model for a SiC MOSFET4Edward Rawde
27 May 25 `* Re: LTSpice model for a SiC MOSFET14Joe Gwinn

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