Re: LTSpice model for a SiC MOSFET

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Sujet : Re: LTSpice model for a SiC MOSFET
De : erichpwagner (at) *nospam* hotmail.com (piglet)
Groupes : sci.electronics.design
Date : 22. May 2025, 19:46:24
Autres entêtes
Organisation : A noisesome patent Spinner
Message-ID : <100nre1$3jb9p$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9
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On 22/05/2025 2:41 pm, Bill Sloman wrote:
On 22/05/2025 8:43 pm, piglet wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
On 22/05/2025 11:20 am, KevinJ93 wrote:
On 5/21/25 12:20 AM, Bill Sloman wrote:
On 21/05/2025 3:47 am, KevinJ93 wrote:
On 5/20/25 1:46 AM, Bill Sloman wrote:
On 20/05/2025 1:13 am, Liz Tuddenham wrote:
Bill Sloman <bill.sloman@ieee.org> wrote:
>
I'm looking at a problem where somebody wants to step down a 1kV low
current source to 3.3V.
>
The Baxandall class-D oscillator could do it, but it needs a pair
1.7kV
MOSFETs for the job. The Infineon SiC IMH170R450M1 would do it -
though
it's a much higher current part (10A) than the job needs (about 1mA).
>
I've dived into the Infineon rabbit-hole which promises LTSpice
models,
but wasn't able to find one.
>
Does anybody know of a similar - ideally cheaper and smaller -
part for
which there is an LTSpice model?
>
How about a piezoelectric transformer run in reverse?
>
The piezoelectric transformer is an interesting idea.
>
Neon tubes illuminating a solar cell?
>
Neither is all that efficient.
>
Capacitive divider using a spare core in the
mains supply lead as one plate of the capacitor?  (Depending on supply
frequency and required output current.)
>
I can't see how that could work. Charging up lots of capacitor is
series, and discharging them in parallel is one mode of current
multiplication, but about the only kind of switch that would work
would be a reed relay, and they are slow and don't last long when
cycled fast.
>
Dry reeds are good for 10 million closures, mercury-wetted reeds for
about 100 million, and neither is all that cheap or compact.
>
>
The Art of Engineering #3 (I think) - describes a "Reverse Marx
Generator" that does exactly that (charging caps in series and
discharging in parallel). It uses diodes as the switching element.
>
The forward diode drop is inconsequential at 1kV, but inconvenient at
3.3V. And you'd need 250 stages in this application.
>
I've got AOE3. It's index doesn't point to any "reverse Marx generator".
Google search throws up links, but nothing useful.
>
The classic Marx generator uses spark gaps as its switches. I have
used them myself (to start a xenon arc lamp), but they wouldn't be
useful here.
>
>
Sorry -- it is on page 440 of the X-chapters, not AOE3.
>
The reverse Marx generator doesn't need to go all the way down to 3.3V
it could just increase the current and reduce voltage to the point where
a conventional converter (such as a flyback) can be used without
excessive voltage devices being used.
>
The Baxandall inverter looks as if it would work with sufficiently high
voltage MOSFET, which clearly exist, even if Infineon is being slow to
offer a Spice model to let me simulate it.
>
It's a pretty simple circuit, even if the component parts look to be on
the expensive side - coping with even 1kV costs money.
>
>
Maybe a simple self oscillating two transistor half bridge as in CFL
ballasts of a few decades ago?
 That's an exact (if incomplete) description  of the Baxandall Class-D oscillator.
 It has got two two transistors and it is self-oscillating, and Jim Williams did popularise it for driving CFL backlights. He never called it a Baxandall oscillator, but that's exactly what his Linear Technology application notes  AN45, AN49, AN51, AN55, AN61, and AN65 talked about.
 
There is a big difference in the voltage stress seen by the transistors.
The half bridge exposes each to 1kV max, the push-pull to nearly double (I think you quoted 1.6kV).
Baxandall topology was great for tape recorder erase/bias oscillator kinda stuff at low supply voltages but at HV not such a great choice.
https://images.app.goo.gl/4xehqS9Kv5udm7uPA
piglet

Date Sujet#  Auteur
18 May 25 * LTSpice model for a SiC MOSFET125Bill Sloman
18 May 25 +* Re: LTSpice model for a SiC MOSFET62john larkin
19 May 25 i`* Re: LTSpice model for a SiC MOSFET61Bill Sloman
19 May 25 i +* Re: LTSpice model for a SiC MOSFET34john larkin
19 May 25 i i`* Re: LTSpice model for a SiC MOSFET33Bill Sloman
19 May 25 i i +* Re: LTSpice model for a SiC MOSFET16john larkin
19 May 25 i i i`* Re: LTSpice model for a SiC MOSFET15Bill Sloman
19 May 25 i i i `* Re: LTSpice model for a SiC MOSFET14Edward Rawde
19 May 25 i i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May 25 i i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i i  `* Re: LTSpice model for a SiC MOSFET11Bill Sloman
20 May 25 i i i   `* Re: LTSpice model for a SiC MOSFET10Mike Perkins
20 May 25 i i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i i i     `* Re: LTSpice model for a SiC MOSFET [OT]8Liz Tuddenham
21 May 25 i i i      `* Re: LTSpice model for a SiC MOSFET [OT]7legg
21 May 25 i i i       +* Re: LTSpice model for a SiC MOSFET [OT]5Liz Tuddenham
21 May 25 i i i       i`* Re: LTSpice model for a SiC MOSFET [OT]4john larkin
21 May 25 i i i       i +* Re: LTSpice model for a SiC MOSFET [OT]2Phil Hobbs
21 May 25 i i i       i i`- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
21 May 25 i i i       i `- Re: LTSpice model for a SiC MOSFET [OT]1Liz Tuddenham
21 May 25 i i i       `- Re: LTSpice model for a SiC MOSFET [OT]1Bill Sloman
19 May 25 i i `* Re: LTSpice model for a SiC MOSFET16Edward Rawde
19 May 25 i i  +* Re: LTSpice model for a SiC MOSFET2john larkin
20 May 25 i i  i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i  `* Re: LTSpice model for a SiC MOSFET13Bill Sloman
20 May 25 i i   `* Re: LTSpice model for a SiC MOSFET12Edward Rawde
20 May 25 i i    +- Re: LTSpice model for a SiC MOSFET1john larkin
20 May 25 i i    +- Re: LTSpice model for a SiC MOSFET1John R Walliker
20 May 25 i i    `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i i     `* Re: LTSpice model for a SiC MOSFET8Edward Rawde
21 May 25 i i      `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May 25 i i       `* Re: LTSpice model for a SiC MOSFET6Edward Rawde
21 May 25 i i        +- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i        `* Re: LTSpice model for a SiC MOSFET4john larkin
21 May 25 i i         +* Re: LTSpice model for a SiC MOSFET2Edward Rawde
21 May 25 i i         i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i         `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May 25 i +* Re: LTSpice model for a SiC MOSFET20legg
19 May 25 i i+* Re: LTSpice model for a SiC MOSFET11Bill Sloman
19 May 25 i ii`* Re: LTSpice model for a SiC MOSFET10legg
20 May 25 i ii `* Re: LTSpice model for a SiC MOSFET9Bill Sloman
20 May 25 i ii  `* Re: LTSpice model for a SiC MOSFET8legg
20 May 25 i ii   +* Re: LTSpice model for a SiC MOSFET4john larkin
20 May 25 i ii   i`* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i ii   i `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May 25 i ii   i  `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i ii   `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i ii    `* Re: LTSpice model for a SiC MOSFET2legg
21 May 25 i ii     `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i i`* Re: LTSpice model for a SiC MOSFET8john larkin
20 May 25 i i `* Re: LTSpice model for a SiC MOSFET7Bill Sloman
26 May 25 i i  `* Re: LTSpice model for a SiC MOSFET6Cursitor Doom
26 May 25 i i   +* Re: LTSpice model for a SiC MOSFET2john larkin
26 May 25 i i   i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
26 May 25 i i   `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
26 May 25 i i    `* Re: LTSpice model for a SiC MOSFET2Cursitor Doom
27 May 25 i i     `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
25 May 25 i `* Re: LTSpice model for a SiC MOSFET6JM
26 May 25 i  `* Re: LTSpice model for a SiC MOSFET5Bill Sloman
26 May 25 i   `* Re: LTSpice model for a SiC MOSFET4JM
26 May 25 i    `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
27 May 25 i     `* Re: LTSpice model for a SiC MOSFET2JM
28 May 25 i      `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
18 May 25 +- Re: LTSpice model for a SiC MOSFET1legg
18 May 25 +* Re: LTSpice model for a SiC MOSFET6legg
19 May 25 i`* Re: LTSpice model for a SiC MOSFET5Bill Sloman
19 May 25 i `* Re: LTSpice model for a SiC MOSFET4legg
19 May 25 i  `* Re: LTSpice model for a SiC MOSFET3Bill Sloman
19 May 25 i   `* Re: LTSpice model for a SiC MOSFET2legg
20 May 25 i    `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
19 May 25 +* Re: LTSpice model for a SiC MOSFET37Liz Tuddenham
19 May 25 i+* Re: LTSpice model for a SiC MOSFET7john larkin
22 May 25 ii`* Re: LTSpice model for a SiC MOSFET6Liz Tuddenham
22 May 25 ii `* Re: LTSpice model for a SiC MOSFET5john larkin
22 May 25 ii  `* Re: LTSpice model for a SiC MOSFET4Liz Tuddenham
22 May 25 ii   `* Re: LTSpice model for a SiC MOSFET3john larkin
23 May 25 ii    `* Re: LTSpice model for a SiC MOSFET2Liz Tuddenham
23 May 25 ii     `- Re: LTSpice model for a SiC MOSFET1john larkin
20 May 25 i`* Re: LTSpice model for a SiC MOSFET29Bill Sloman
20 May 25 i +* Re: LTSpice model for a SiC MOSFET8Liz Tuddenham
20 May 25 i i`* Re: LTSpice model for a SiC MOSFET7Bill Sloman
21 May 25 i i `* Re: LTSpice model for a SiC MOSFET6Liz Tuddenham
21 May 25 i i  +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
21 May 25 i i  i`* Re: LTSpice model for a SiC MOSFET2Liz Tuddenham
21 May 25 i i  i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
21 May 25 i i  `* Re: LTSpice model for a SiC MOSFET2john larkin
21 May 25 i i   `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
20 May 25 i `* Re: LTSpice model for a SiC MOSFET20KevinJ93
21 May 25 i  `* Re: LTSpice model for a SiC MOSFET19Bill Sloman
22 May 25 i   `* Re: LTSpice model for a SiC MOSFET18KevinJ93
22 May 25 i    +* Re: LTSpice model for a SiC MOSFET8Bill Sloman
22 May 25 i    i`* Re: LTSpice model for a SiC MOSFET7piglet
22 May 25 i    i +* Re: LTSpice model for a SiC MOSFET3Bill Sloman
22 May 25 i    i i`* Re: LTSpice model for a SiC MOSFET2piglet
23 May 25 i    i i `- Re: LTSpice model for a SiC MOSFET1Bill Sloman
22 May 25 i    i +* Re: LTSpice model for a SiC MOSFET2john larkin
22 May 25 i    i i`- Re: LTSpice model for a SiC MOSFET1Bill Sloman
23 May 25 i    i `- Re: LTSpice model for a SiC MOSFET1legg
27 May 25 i    `* Re: LTSpice model for a SiC MOSFET9john larkin
27 May 25 i     `* Re: LTSpice model for a SiC MOSFET8Bill Sloman
27 May 25 i      `* Re: LTSpice model for a SiC MOSFET7Liz Tuddenham
19 May 25 +* Re: LTSpice model for a SiC MOSFET4Edward Rawde
27 May 25 `* Re: LTSpice model for a SiC MOSFET14Joe Gwinn

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