Re: LTSpice model for a SiC MOSFET

On 27/05/2025 11:46 pm, john larkin wrote:

On Tue, 27 May 2025 14:16:11 +0100, liz@poppyrecords.invalid.invalid
(Liz Tuddenham) wrote:
 

Bill Sloman <bill.sloman@ieee.org> wrote:
>

On 27/05/2025 9:09 am, john larkin wrote:

>
[...]

The specs, as far as I can tell, suggest 1KV at 1 ma in and 3.3v at 3
ma out. The required efficiency is then 1%.

>
Actually 1kV at 10uA in.

>
Good grief!   A 10-megohm quarter watt resistor with a zener diode is
the obvious answer.

 A 3.3v real zener will probably leak more than 10uA. Low voltage
zeners are awful.
 And he wants 3 mA out... I think.

The guy I was talking to had 10uA at 1kV, and wanted a 3.3V output. 1mW at 3.3V is 3mA. The 3ma is the upper limit the circuit could supply.

>
[...]

Misunderstanding the constraints can lead people to propose
inappropriate solutions.

>
How can anyone misunderstand something they have never been told?

You managed it.

Bill was the confused person.

John Larkin does like to think that.

The problem gets much more interesting with 10 uA in and 99%
efficiency requirement.

There never was an efficiency requirement. 50% would have been nice.

A Baxandall isn't going pull microamps at 1 KV.

Keeping a resonant tank resonating at a couple of kV is going to use up power in the winding resistance. I think I can get 245H out of RM14 core. If we can keep the parallel capacitance down to 25pF that would resonate at 2kHz and the reactive impedance would be 3 Mohm, giving a peak current 0f 1mA. The resistance of the winding is going to be about 480R, so I^2.R is 500uW, or 0.5uA at 1kV.
A properly designed Baxandall might well pull less than 1uA if lightly loaded.
--
Bill Sloman, Sydney