Re: LTSpice model for a SiC MOSFET

On 28/05/2025 4:09 am, JM wrote:

On Tue, 27 May 2025 02:43:41 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
 

On 27/05/2025 1:57 am, JM wrote:

On Tue, 27 May 2025 01:07:36 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>

On 26/05/2025 4:20 am, JM wrote:

On Mon, 19 May 2025 12:23:54 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>

On 19/05/2025 12:15 am, john larkin wrote:

On Sun, 18 May 2025 18:11:58 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:

<snip>

I have found a 4.5KV MOSFET, the IXYS IXTT02450HV which could survive in
the standard Baxandall configuration.
>
It's $US45.24 each in small volume (which really is excessively
expensive), and I've asked for Spice model, but if Infineon is anything
to go by, I'm not going to get it anytime soon.
>
If either Spice model shows up I'll try and put a simulation together.
It has nearly got to the point where I should try and bodge a MOSFET
model that I have got access to into something that would fit one or
other data sheet, but that's hard work, and my model isn't going to be
all that trustworthy.

 You are probably best with bipolar.  If you use a push-pull current
fed half bridge the transistor breakdown rating will be 500*PI (1.57
kV).  Since the off transistor will have a reverse bias of a few volts
on it's base it's breakdown voltage will (typically) be a few hundred
volts greater than it's Vceo spec.  The 2sc4634/4636 would suffice.

Since IXYS has just now come up with a PSpice model - a sub-circuit model - for the IXTH02N450HV - I'll probably take the path of least resistance and see if I can get that to work.
Right now I'm going to bed.
--
Bill Sloman, Sydney