Re: LTSpice model for a SiC MOSFET

On 30/05/2025 4:23 am, john larkin wrote:

On Thu, 29 May 2025 16:12:52 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
 

On 29/05/2025 3:56 am, john larkin wrote:

On Thu, 29 May 2025 02:24:01 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>

On 29/05/2025 12:26 am, john larkin wrote:

On Wed, 28 May 2025 21:03:03 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
>

On 28/05/2025 3:08 am, Joe Gwinn wrote:

On Tue, 27 May 2025 07:53:12 -0700, john larkin <jl@glen--canyon.com>
wrote:
>

On Tue, 27 May 2025 10:02:27 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:
>

On Tue, 27 May 2025 20:32:49 +1000, Chris Jones
<lugnut808@spam.yahoo.com> wrote:
>

On 18/05/2025 6:11 pm, Bill Sloman wrote:

<snip>

He does want it to be inexpensive. There doesn't seem to be any
specialised market where a few customers can afford to pay a lot of
money for a few devices, or if there is he hasn't mentioned it to me
(and probably wouldn't) if there was.

 I can imagine some cheap approaches if something like 25% efficiency
were acceptable.

I finally got a Pspice model for the IXTH02N450HV out of IXYS and - with a bit of help from John May - got the part working in a simulation.
I did managed to get 1mA out at 3.3V but I was drawing 12.5uA out of the 1kV source, so only about 30% efficiency. The two transistor are $US45 each, so it's not a cheap circuit. It only runs at 2.5kHz even with pretty optimistic parallel capacitances for the high impedance windings.
There a 40kHz ripple on the current drawn from the 1kV suuply at about 115uA peak to peak, so that may be where the extra current is being used up.
--
Bill Sloman, Sydney