Re: LTSpice model for a SiC MOSFET

On 3/06/2025 11:05 pm, legg wrote:

On Tue, 3 Jun 2025 11:58:30 +1000, Bill Sloman <bill.sloman@ieee.org>
wrote:
 

On 3/06/2025 2:42 am, legg wrote:

<snip>

>

He does want it to be inexpensive. There doesn't seem to be any
specialised market where a few customers can afford to pay a lot of
money for a few devices, or if there is he hasn't mentioned it to me
(and probably wouldn't) if there was.

>
I can imagine some cheap approaches if something like 25% efficiency
were acceptable.

>
I finally got a Pspice model for the IXTH02N450HV out of IXYS and - with
a bit of help from John May - got the part working in a simulation.
>
I did managed to get 1mA out at 3.3V but I was drawing 12.5uA out of the
1kV source, so only about 30% efficiency. The two transistor are $US45
each, so it's not a cheap circuit. It only runs at 2.5kHz even with
pretty optimistic parallel capacitances for the high impedance windings.
>
There a 40kHz ripple on the current drawn from the 1kV suuply at about
115uA peak to peak, so that may be where the extra current is being used up.

>
So it's 3V3 at 1mA, after all.
>
2W resistor and a zener diode.

>
The 1kV source is good for about 10uA. Do pay attention.

 If you'd answered those questions accurately, when originally asked,
you would have had my attention.

If you look at the subject line of the thread, you will note that I was after Pspice model for a particular transistor. I did mention that the 1kV source was "low current" - and I wanted to step it down to to 3.3V, fairly obviously by using a switching circuit.
If you'd care to quote the questions you asked, and post a couple of my "inaccurate answers" I might take you seriously, but you've asserted that I was acting like a troll on several occasions, so it is unlikely.
--
Bill Sloman, Sydney