Sujet : Re: reset circuit
De : jl (at) *nospam* glen--canyon.com (john larkin)
Groupes : sci.electronics.designDate : 07. Jun 2025, 21:46:30
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <8p894k17crcqf3hug8gas091d7vgj01idu@4ax.com>
References : 1 2
User-Agent : ForteAgent/8.00.32.1272
On Sat, 7 Jun 2025 12:29:06 -0700, John Robertson <
jrr@flippers.com>
wrote:
On 2025-06-07 9:41 a.m., john larkin wrote:
We have a box that has to never make any false outputs. Bad things
could happen.
Part of the fix is to have a solid powerup reset signal, to handle
power brownouts or such. This looks OK:
https://www.dropbox.com/scl/fi/cejyyhcrdph1bewn8a6nx/P800_Reset_1.jpg?rlkey=leky75poeerbojmd3xjat4z54&raw=1
The 12 and 5v rails will have a bunch of downstream bypass caps. The
dump resistors will discharge them.
>
Did you allow for the voltage drop across the transistor in your Reset
Supervisor selection?
>
Just asking...
>
John :-#)#
Sure. In normal operation it's inverted-state saturated, so the MAX
part sees all the +5.
If the +12 dips to about +10, the transistor base is +5, and the
emitter is 4.4, and the MAX says reset.
That transistor has an insane beta and a pretty hunky inverted beta.