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On Fri, 10 May 2024 17:27:10 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:
Or skip to the end and only invent AVX while skipping the soon-to-be
redundant intermediate stages.
Well, I went to 256-bit short vectors as a permanent part of the
architecture, with long vectors as the next step.
But what about crypto assist instructions, as another example?If used often enough, sure, they make a lot of sense--just make whatever
However, I think I will adjust this feature. You comlained I used up
too much of my opcode space, so I demonstrated that Concertina II had
the potential to have... a _lot_ of opcode space, even to ludicrous
lengths.
Now that I think I can finally wrap up Concertina II, having found howWould you like to read My 66000 ISA while taking a break between CT II and
to achieve its goals as best as possible, I can go on to Concertina
III... and, given your anguished pleas, I _will_ give up on block
structure for the next iteration.
In order to do that, though, it will have to be CISC, not RISC...With MEM-OPs are you not already CISC ??
banks of 8 registes, sort of like Concertina I, but much less messy.
John Savard
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