Re: MSI interrupts

On Tue, 25 Mar 2025 15:10:19 +0000, Dan Cross wrote:

In article <b201b9212700f9359a831e03b1d60cef@www.novabbs.org>,
MitchAlsup1 <mitchalsup@aol.com> wrote:

On Tue, 25 Mar 2025 13:45:39 +0000, Scott Lurndal wrote:
>

mitchalsup@aol.com (MitchAlsup1) writes:

>

Nothing gets lost.

>
This isn't a hardware transaction.   If the thread has updated data
and you take away the lock, the system is now inconsistent
and nasal daemons will ensue.

>
In HW there is a little thing known as branch misprediction repair,
where all the work done is made to appear as if those instructions
were never executed to begin with. The size of the branch mispredict
window is on the order of 300 instructions now.
>
With Spectré and Meltdown even cache updates must be delayed until
after the causing instruction retires.

>
But again, that's irrelevant.  The "critical sections" in
question here are software abstractions created by system
software.

Say you have a critical section (of your description) that was
preceded by an if-statement that was predicted to enter CS, but
1,000 cycles later the branch is resolved to not enter the CS.
{{Branch was dependent on an MMI/O location down the PCIe tree
which is why it took so long to resolve.}}
HW Backs the core up so that the RF and all memory locations
contain their original values at the point of the mispredicted
branch.
Can thread running on core even tell if you entered CS or not !
No, your thread cannot.