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MitchAlsup1 <mitchalsup@aol.com> wrote:If you put cache write at or after register file write in theOn Tue, 20 Aug 2024 17:40:50 +0000, Michael S wrote:>
>On Tue, 20 Aug 2024 16:40:06 +0000>
mitchalsup@aol.com (MitchAlsup1) wrote:
>>>
and you may have
several of these in a local sequence of code. ...
No, you can not have several. It's always one then another one then yet
another one etc... Each one can reuse the same temporary register.
The point is that the cost of not getting allocated into a register
is vastly lower--the count of instructions remains 1 while the
latency increases. That increase in latency does not hurt those
use once/seldom variables.
>
The the examples cited, the lack of register allocation triples
the instruction count due to lack of LD-OP and LD-OP-ST. The
register count I stated is how many registers would a
non-LD-OP machine need to break even on the instruction count.
>
LD-OP-ST is a bridge too far for me.
>
LD-OP and OP-ST are fine with me and have benefits.
But you have not built such, you built an improved RISC…I spent 7 years doing x86-64.....so much for not having.....
I assume OP-ST has issues with the value getting stuck if the address isAthlon and Opteron had value capturing reservation stations.
slow to resolve. With a register the value can just spill to the
register backing file. And because of this you create a hidden register
name for the value.
You have information on how many hidden registers are in flight onPartially because AMD performed "relatively" better on LD-OPs and
average and worst case, so I believe your numbers.
>
I have not looked to see if compilers generate LD-OP and OP-ST, at one
point Intel was discouraging such code.
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