Re: Memory ordering

On Thu, 1 Aug 2024 15:54:55 +0000, Anton Ertl wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

On Tue, 30 Jul 2024 9:51:46 +0000, Anton Ertl wrote:
>

mitchalsup@aol.com (MitchAlsup1) writes:

>

An MEMBAR requires the memory order to catch up to the current point
before adding new AGENs to the problem space. If the memory order
is already SC then MEMBAR has nothing to do and is pushed through
the pipeline without delay.

>
Yes, that's the slow implementation.  The fast implementation is to
implement sequential consistency all the time (by predicting and
speculating that memory accesses do not interfer with those of other
cores, and recovering from that speculation when the speculation turns
out to be wrong).  In such an implementation memory barriers are noops
(and thus fast), because the hardware already provides sequential
consistency.

Why does SC need any MEMBARs ??

Then consider 2 Vector processors performing 2 STs (1 each) to
non-overlapping addresses but with bank aliasing. Consider that
the STs are scatter based and the back conflicts random. There
is no way to determine which store happened first or which
element of each vector store happened first.

>
It's up to the architecture to define the order of stores and loads of
a given core.  For sequential consistency you then interleave the
sequences coming from the cores in some convenient order.

Insufficient:: If OoO processor orders LDs and STs as they leave AGEN
you cannot just interleave multiple core access streams and achieve
sequential consistency.

                                                          It does not
matter what happens earlier in some inertial system.  It only matters
what your hardware decides should be treated as being earlier.  The

Causal consistency is determined by arrival order at the memory
controller.
Cache consistency is enforced by allowing a single line to be "in
progress"
only once in the system--each cache line is serially reusable, while
other
cache liens remain unordered wrt that one.

hardware has a lot of freedom here, but the end result as visible to
the cores must be sequentially consistent (or, with a weaker memory
consistency model, consistent with that model).
>
- anton