Re: Scan chains

On Wed, 7 May 2025 3:12:08 +0000, Stefan Monnier wrote:

Even state-of-the-art CPUs today commonly use scan-chains (via JTAG)
for debuggin.

Is there some blog somewhere that explains how scan-chains work (not
how they're used, but how they're implemented inside the CPU)?
Intuitively they sound very costly to me, because of things like the
need to run extra wires all over the place.  I'm obviously
missing something.

Actually, you're not far off.  It's a serial shift chain which is
shifted
one-bit at a time to capture flop states.  Each chain is a single wire;
a chip may have a few dozen individual shift chains.
https://www.design-reuse.com/articles/48331/scan-chains-pnr-outlook.html

>
Thanks.  Wow.  So it is really that bad, huh?
I also liked the note about speed limits and power consumption, how
shifting a state (in or out) causes (almost) all the flip-flops to
change state at each cycle, thus leading to very high power consumption.

two (2) things::
a) the scan path is only used when the rest of the logic is quiescent.
..in normal operation it is but fan-in load to the flip-flops.
b) the scan clock is typically around 200 MHz
Both eliminate the power consumption problem.
Remember it is going to take ~5,000 scan-clocks to scan out/in a core.
Scan paths en-the-large operate at human visualization frequencies.

What's the approximate cost of those scan chains.  I.e. if we were to
take an existing working design and replace all the "flip-flop with
scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power
could it consume?

Given a 16-gate delay design with 5 gates of "flop-jitter-skew"
the scan path adds about ½ a gate of delay (2%-ish).

I assume the cost in terms of power consumption is small because in
normal use, the scan-chain part stays completely stable so that barring
leakage it should not consume any power, save for the indirect costs
like the need to move the other bits over greater distances when
the extra wires of the scan chains get in the way.

As far as power consumption of the extra logic is concerned when not
being used; it is also down in the 1% range (maybe lower).

>
        Stefan