Sujet : Re: PCIe MSI-X interrupts
De : already5chosen (at) *nospam* yahoo.com (Michael S)
Groupes : comp.archDate : 27. Jun 2024, 09:27:20
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <20240627112720.00005063@yahoo.com>
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On Thu, 27 Jun 2024 01:47:49 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:
Exactly what are you intending to mean from "single-copy atomic
accesses" ??
It sounds as a politically correct way of saying "default memory
ordering of ARMv8.1-A and later".
I.e. weaker than x86-64 and SPARC TSO, but stronger than Itanium.
Probably stronger than POWER, but I am not sure if POWER ever had memory
ordering model formalized.
PCIe MSI-X interrupts
Re: PCIe MSI-X interrupts