Re: arm ldxr/stxr vs cas

On Sun, 08 Sep 2024 18:32:42 GMT
scott@slp53.sl.home (Scott Lurndal) wrote:

Michael S <already5chosen@yahoo.com> writes:

On Sun, 08 Sep 2024 16:10:41 GMT
scott@slp53.sl.home (Scott Lurndal) wrote:
 

 
On AMD processors (and likely intel), if a core cannot acquire
a cache line in a a finite time, the core will assert the bus lock
to ensure forward progress.
 
Nothing to do with the operating software;  purely a hardware
thing. 

>
>
I think, on AMD processors made in this century the only cases that
resort to physical bus lock are
A) atomic accesses that cross cache boundary
B) atomic accesses that address non-cached memory regions 

 
C) A core cannot acquire a cache line in a finite time.  We
   encountered this in 2010 on AMD Opteron processors with
   our HyperTransport connected CXL-like chip (designed in 2005);
   r/t latency could be as high as 800ns to remote memory.
 

PathScale Infinipath, I suppose.

Bought by QLogic then sold to Sicortex then picked by Cray when
Sicortex went belly-up then resold to Intel where it became the base
for Omni-Path that was discontinued in 2019, but according to Wikipedia
still living under Cornelis Networks.
https://www.cornelisnetworks.com/

I never liked attempts to use it as cache-coherent interconnect.