Re: is Vax addressing sane today

On Tue, 10 Sep 2024 08:05:07 GMT
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

John Levine <johnl@taugh.com> writes:
 

Compare that to zSeries, where even after 50 years of sticking new
instructions into the holes in the S/360 instruction set, it can
still tell the length of the instruction from the first two bits and
the operands from the first byte. 

 
Good for sequential decoding, and maybe it makes parallel decoding
cheaper (but OTOH, the first superscalar S/360 descendent came out in
2000, 7 years after the superscalar Pentium, and the first OoO S/360
descendent lagged the Pentium Pro by 14 years or so),

Wikipedia says that ES/9000 Model 900 had superscalar OoO CPU in 1991.
This line was abandoned in favor of simpler 'CMOS' line in mid 90s, but
according to the same Wiki article, CMOS line didn't matched Model 900
in performance until 9672-RY5 near the end of 1997.

but as the IIRC
6-wide decoder of Alder Lake demonstrates, hardware designers are able
to deal with instruction sets that do not have such nice properties:
an AMD64 instruction can have a large number of prefixes, and I think
that the encoding of indexed addressing is not announced in the first
non-prefix instruction byte, either.
 
- anton

1. The longest AMD64 instruction is much shorter than the longest VAX
instruction
2. On AMD64 instruction length information is continuous. Yes, there
could be multiple prefixes and it makes things ugly, but I would think
that in practice you very rarely need to look at more than 5 leading
bytes in order to figure out the length of the tail. And in practice
it's probably o.k. when instructions with more than 3 prefixes decoded
slowly.