Sujet : Re: Interview with Power's chief designer
De : already5chosen (at) *nospam* yahoo.com (Michael S)
Groupes : comp.archDate : 29. Dec 2024, 13:29:19
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <20241229142919.000014a6@yahoo.com>
References : 1
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On Fri, 27 Dec 2024 13:29:22 -0000 (UTC)
Thomas Koenig <
tkoenig@netcologne.de> wrote:
Not sure how many of you read Chips and Cheese, but in case you're
interested: Here is an inteview with IBM Power's chief designer,
Bill Starke:
https://old.chipsandcheese.com/2024/12/26/ibm-power-whats-next/
Why no editing?
Why do I have to see 100 repetitions of "you know" ?
And, BTW, Danish blue is a poor substitute for Roquefort. Even Pecorino
blue is better.
There is a lot of talk on OMI (he really doesn't like DDR, and gives
reasons, especially the amount of memory and reliability),
I didn't understand this part. My understanding of Power10 and supposed
of Power11 memory architecture is that ideologically it is the same as
Intel'a Beckton and Westmere-EX of early 2010s. Of course, everything
is beefier than it was then - there are more links and each link runs
4x to 5x faster than on Beckton. But basic principle is the same, what
Intel called Buffers-on-Board (BoB). I.e. fast link runs from CPU
through either PCB or possibly cable to distance of 1-3 cm from where
they place memory. At this point the is a buffer chip that translates
fast protocol to several industry-standard DDR buses. In Intel's case
there were 2 buses. In POWER10 cases probably 3 or 4. Buffers used by
Power10 supposedly supported both DDR4 and DDR5. I would expect that
DDR5 is the only remaining option for POWER11.
But the point is that behind the buffer chips they have the same DIMMs
as everybody else with the same poor edge connectors that cause the same
signal integrity and reliability problems.
plus some
detail on POWER11, which apparently will be a microarchitectural
evolution, but no new ISA parts, and the philosophy behind the
chiplet design they are about to do for the next generation after
that.
I read it differently. Like POWER11 is already made out of one IO
chiplet and several compute chiplets.
Apparently, nobody knows what its name will be, but it might
be something like "Power 11 plus one".