Re: Instruction Tracing

John Levine <johnl@taugh.com> writes:

As far as the delayed branches and such, they made sense in the narrow
time window when it was too expensive to put a cache on a workstation
but that time came and went by the time the RT shipped.

Delayed branches were put in the first commercial generation of RISCs
(except ARM), which all shipped with caches (except ARM).  Delayed
branches are a natural consequence of the 5-stage (Or, in the 88100
case, four-stage) pipeline.

IIRC ARM used a 3-stage implementation for the ARM1/2, which may be a
consequence of them rejecting delayed branches; and they did not have
caches, so they could not have made use of the higher clock rate that
a longer pipeline could have affored.  So it seems that the connection
between cache and delayed branches, if there is any, is the opposite
of what you suggest.

Delayed branches provided a speedup on these early 5-stage
implementations.  They also provided a big headache for more
sophisticated implementations, and therefore soon fell out of favour.
Power (IIRC) and Alpha don't have delayed branches.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>