Re: My 66000 and High word facility

mitchalsup@aol.com (MitchAlsup1) writes:

On Sun, 11 Aug 2024 14:33:33 +0000, Anton Ertl wrote:
>

Brett <ggtgp@yahoo.com> writes:

The lack of CPU’s with 64 registers is what makes for a market, that 4%
that could benefit have no options to pick from.

>
They had:
>
SPARC: Ok, only 32 GPRs available at a time, but more in hardware
through the Window mechanism.

>
SPARCs FPGA through UltraSPARC used 1 full cycle to access the windowed
register file will MIPS, 88K, and early Alphas used 1/2 cycle.

Maybe.  Obviously did not prevent them from having ALU instructions
with one-cycle latence and loads with 2-cycles latency in the early
implementations, just like MIPS R2000.  And the clock rate of the
SPARC MB86900 (14.28MHz) is not worse than the clock rate of the MIPS
R2000 (8.3, 12.5, and 15MHz grades), and that despite having the
interlocks that MIPS were so proud of not having.

Oh, and BTW, that 1/2 cycle of delay getting started should have cost
~5% IPC. But SAPRC never achieved high clock frequencies nor dis IA-64.

As mentioned above, the clock rate was competetive with the early
MIPS.  If we look at more recent times, the in-order UltraSPARC IV+
(90nm) achieved 2100MHz in 2007; Intel sold 3GHz 65nm Core 2 Duo E6850
at the time, so the UltraSPARC IV+ was not that far off.  This
undermines my theory that in-order designs have problems achieving
high clock rates.

Going for OoO implementations, the Fujitsu SPARC64 V+ (90nm) was
shipped in 2004 with 1.89MHz and in 2006 with 2.16MHz.  AMD shipped
the 2.2GHz Athlon 64 3500+ (90nm) in 2004 and a 2.4GHz 90nm version in
2006, so the SPARC64 V+ was not far off.

Fujitsu continued their line until the 4.25GHz SPARC64 XII in 2017.
For comparison: AMD released the Ryzen 1800X in 2017 and that
supposedly can turbo up to 4GHz (but when I just measured it (with 1
core loaded), it achied <3.7GHz).  Intel sold the Core i7-8700K
starting on Oct 5, 2017, which achieved 4.7GHz.

Oracle released the 5000MHz SPARC M8 in 2017.

Maybe SAPCR (sic!) did not achieve high clock rates, but SPARC did.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>