Re: Chipsandcheese article on the CDC6600

mitchalsup@aol.com (MitchAlsup1) writes:

If hardware branch prediction had never been invented or had turned
out to be a dud, maybe we would all be using EPIC architectures that
use scoreboards rather then reservation stations; or maybe the

>
CDC 7600 predicted backwards branches to be taken

That's a primitive form of compiler branch prediction.  More advanced
schemes had a direction hint in the instruction.  These schemes are
not hardware branch prediction as far as "compiler vs. hardware branch
prediction" is concerned.

register interlocks that were used in advanced in-order RISCs (those
that Mitch Alsup calls OoO) and AFAIK in IA-64 implementations were
good enough and one would have done without scoreboard.

>
Register interlocks is the means to allow GHW to move instructions
around in the pipeline--you just have to obey RAW, WAR, and WAW
hazards.

What is GHW?  Stanford MIPS and most of MIPS R2000/R3000 moved
instructions in the pipeline without interlocks.  It's in their name:
Microprocessor without interlocked pipeline stages.

[*] More supercomputing-oriented people may claim that it has to do
with the number of in-flight memory accesses, but actually IA-64 shone
on SPEC FP (where in-flight memory accesses are more important than
for SPECint), so it seems that there are ways to get the needed
in-flight memory accesses with in-order execution.

>
IA-64 had 2× the number of pins compared to its x86 brethren.
No wonder it could consume more BW.

Did not help it a bit with integer code.  If the myth was true that
only OoO enables many in-flight memory accesses, it would not help for
bandwidth-hungry code, either.  The fact that IA-64 implementations
could make use of the bandwidth busts that myth.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>