Re: Privilege Levels Below User

EricP <ThatWouldBeTelling@thevillage.com> writes:

PAL code is stored an a writable control store that
is a separate address space from main memory

Given the way that it (the EV45 PAL code) implements the PAL-call IMB,
i.e., by executing enough code to flush the I-cache, means that the
PAL-code is loaded into the I-cache, so I expect that it resides in
normal RAM.  If that was in a separate memory space, there would need
to be an additional bit in each I-cache tag that records this fact.

But I came to realize that none of that is actually *required*.
It doesn't *need* a third privilege mode, and actually it looks
more expensive performance wise to have one than not.
It would be simpler and cheaper to just transition directly
to and from Super mode without also going through PAL mode.
And there is NO technical reason to restrict access to HW control
register from Super mode.
>
Many processors automatically disable interrupts on trap because it
greatly simplifies the race conditions in their prologue and epilogue.
x86 did not disable interrupts on exceptions but x64 allows it as an option.
>
PAL mode does not require its own on-chip SRAM - it could exist in main
memory addressed through a base physical register or an MMU hack.
And having a dedicated private on-chip SRAM to hold critical OS code
does not mean that it is microcode. I would have this for my design
with an MMU fiddle to hard-wire a VA->PA mapping for some OS code.
>
After realizing it didn't need to exist, and that PAL mode looks more
expensive than just User/Super modes, I began to wonder why it was there.
Which leads me to here:
>

(I think PAL mode was a way to patent a feature that made the
ISA impossible to copy without their permission,

Not really.  If there was a patent that is specific to it being a
different address space or a dedicated private on-chip SRAM, that
patent could be easily circumvented by the Amdahl-alike by putting the
PAL-code in RAM and using a base register or MMU hack, as you
describe.

Also if there was enough room for more on-chip SRAM on any of the
Alpha chips, the designers would have used that room to put in
features that make the chip faster.

Given that ARM is able to charge an architecture licensing fee for the
instruction set alone, I am sure that DEC had enough patents on its
instruction set, no need for unnecessary and circumventable
implementation ideas.

One other thing they did: they had one PAL code coming with the SRM
console for VMS and Digital OSF/1, and another PAL code with the
ARC/AlphaBIOS console for Windows NT and Linux.  This allowed them to
charge extra (quite a lot) for hardware capable of running their
premium OSs, while providing almost competetive prices for hardware
running PC OSs.  Unfortunately, the PC-like package was still not
price/performance competetive, and AlphaBIOS (which we had on our EV56
boxes) was a horror to work with.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>