Sujet : Re: architectural goals, Byte Addressability And Beyond
De : anton (at) *nospam* mips.complang.tuwien.ac.at (Anton Ertl)
Groupes : comp.archDate : 05. Jun 2024, 11:32:25
Autres entêtes
Organisation : Institut fuer Computersprachen, Technische Universitaet Wien
Message-ID : <2024Jun5.123225@mips.complang.tuwien.ac.at>
References : 1 2
User-Agent : xrn 10.11
jgd@cix.co.uk (John Dallman) writes:
I would like to keep testing the commercial product I work on in a
big-endian, alignment-trapping environment.
Computer architecture exhibits convergence. Starting in the 1960s it
converged on byte addressing with 8-bit bytes and on 2s-complement,
starting in the 1980s it converged on IEEE FP, and ending in the 2010s
it converged on supporting unaligned accesses and on little-endian
byte order. Your difficulties in getting hardware for testing whether
software can work with alignment restrictions and with big-endian byte
order is a result of that convergence. Maybe your desire to keep your
software ready for big-endian hardware and hardware with alignment
restrictions is misguided.
New SPARC boxes are expensive, dealing with Oracle is hard work, and the
architecture has no future.
Ebay?
- anton
-- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>