Re: is Vax addressing sane today

Brett <ggtgp@yahoo.com> writes:

Speaking of complex things, have you looked at Swift output, as it checks
all operations for overflow?
>
You could add an exception type for that, saving huge numbers of correctly
predicted branch instructions.
>
The future of programming languages is type safe with checks, you need to
get on that bandwagon early.

MIPS got on that bandwagon early.  It has, e.g., add (which traps on
signed overflow) in addition to addu (which performs modulo
arithmetic).  It has been abandoned and replaced by RISC-V several
years ago.

Alpha got on that bandwagon early.  It's a descendent of MIPS, but it
renamed add into addv, and addu into add.  It has been canceled around
the year 2000.

RISC-V, another descendent of MIPS, has an add instruction that
corresponds to MIPS' addu, and no instruction that corresponds to
MIPS' add.  They obviously don't think that there's a bandwagon.  Note
that RISC-V was designed after Swift was introduced.

IA-32 got on that bandwagon early.  It has a single-byte instruction
trapv that traps if the overflow flag is set.  The AMD64 instruction
set is very similar to the IA-32 instruction set, but one of the few
differences is that the trapv instruction was eliminated, and the
encoding replaced with a REX prefix.  The AMD64 architects obviously
don't think that there is a bandwagon.

Apple has been designing their own silicon for a while, and they have
introduced Swift as their language in 2010.  Yet they have not
switched to an architecture like MIPS or Alpha, nor have they designed
their own architecture or architecture extension that includes
instructions like Alpha's addv or IA-32's trapv.  Instead, they
switched to ARM A64, which does not have such features, after
introducing Swift in 2010.  They obviously don't think that there is
such a bandwagon, either.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>