Re: is Vax addressing sane today

Michael S <already5chosen@yahoo.com> writes:

On Tue, 10 Sep 2024 08:05:07 GMT
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

Good for sequential decoding, and maybe it makes parallel decoding
cheaper (but OTOH, the first superscalar S/360 descendent came out in
2000, 7 years after the superscalar Pentium

Correction: The first superscalar CMOS S/360 descendent, the z990 came
out in 2003, a decade after the Pentium, but see below about bipolar
CPUs.

and the first OoO S/360
descendent lagged the Pentium Pro by 14 years or so),

>
Wikipedia says that ES/9000 Model 900 had superscalar OoO CPU in 1991.

Reading up on this, the article says even more:

|models 900 and 820 had full out-of-order execution for both integer
|and floating-point units, with precise exception handling, and a fully
|superscalar pipeline.

So these are probably the first proper OoO processors (while the
360-91 was an interesting prototype, it was too limited to count as
proper OoO CPU).  The 900 ran at 111MHz, and the 1994-vintage 9X2 ran
at 141MHz and was rated at 468MIPS (for 10 CPUs), i.e. each 141MHz CPU
at 47MIPS.  So that would be an IPC of 1/3, which is somewhat
disappointing even for an early superscalar OoO machine.  But then I
don't know how IBM produces its MIPS ratings.

This line was abandoned in favor of simpler 'CMOS' line in mid 90s, but
according to the same Wiki article, CMOS line didn't matched Model 900
in performance until 9672-RY5 near the end of 1997.

A single-issue in-order CPU running at 370MHz with comparable per-CPU
performance (and also 1-10CPUs); apparently 49MIPS for one CPU and
447MIPS for 10.  Again, the IPC seems abysmal, but who knows how IBM
measures MIPS.  Still, I expect that a contemporaneous Pentium II
outperforms this 9672 by a lot on, say, SPEC95, just because of the
basic technology and clock rate.

It seems that during the late 1990s, IBM was not particularly
interested in mainframe per-CPU performance.

1. The longest AMD64 instruction is much shorter than the longest VAX
instruction
2. On AMD64 instruction length information is continuous. Yes, there
could be multiple prefixes and it makes things ugly, but I would think
that in practice you very rarely need to look at more than 5 leading
bytes in order to figure out the length of the tail. And in practice
it's probably o.k. when instructions with more than 3 prefixes decoded
slowly.

Yes, you can always choose to take slow paths on rare cases, but you
can also do that for a VAX decoder.  I don't expect that the 37 bytes
(or whatever it is) is the common case.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>