Re: DRAM Chiplet for L3 cache?

On Mon, 27 Jan 2025 17:18:29 GMT
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:

This brings up the question of why, at least so far, no one is using
a DRAM chiplet (i.e. one made with a DRAM specialized technology),
for the L3 cache.  ISTM that the advantage of being able to put a
much higher capacity cache in the same physical size chiplet is
substantial. 

 
There used to be eDRAM used for an L4 cache ("Crystall Well") in some
Intel Broadwell and Skylake variants, as well as eDRAM used as L3
cache on Power8.

In Power7/8/9 eDRAM is a part of proccessor die, so not quite the same
as OP's suggestion.

In some of IBM's mainframe processors eDRAM is present both as on-die
L2 and L3 caches and as on package L4 cache. I don't remember an exact
number of this CPU.

There is an insightfull article on Crystal Well (as
well as a little bit about Power8):
<https://old.chipsandcheese.com/2024/11/01/broadwells-edram-vcache-before-vcache-was-cool/>,
which also provides an explanation why this technology is no longer
used.
 
In a recent article
<https://old.chipsandcheese.com/2025/01/18/inside-the-amd-radeon-instinct-mi300as-giant-memory-subsystem/>
they look at how a memory-side SRAM cache performs in the MI300A.  For
CPUs you really want to have the cache on the core side.
 
- anton