Re: Why VAX Was the Ultimate CISC and Not RISC

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

On Sat, 01 Mar 2025 22:25:26 GMT, Anton Ertl wrote:
>

The other thing is that the VAX 11/780 (released 1977) had a 2KB cache,
so Bell's argument that caches were only available around 1985 does not
hold water on that end, either.

>
It was about the sizes of the caches

Sure, more cache is better than less cache, all other things being
equal, but as the ARM2 without cache demonstrates, a RISC running out
of RAM can outperform the VAX-11/780 with 2KB (or is it 8KB? see
below) cache.  And as the ARM3 with 4KB cache demonstrates, that
performance advantage increases by a lot with even a 4KB cache.

and hence their contribution to the
cost.

Interestingly,
<http://bitsavers.informatik.uni-stuttgart.de/pdf/datapro/datapro_reports_70s-90s/DEC/M11-384-40_8402_DEC_VAX-11.pdf>
reports VAX-11/780 cache as having 8KB (4KB for the /750).  It also
gives a delivery date of Jan. 1978 for the VAX-11/780.  So that cost
was obviously acceptable for the VAX-11/780, and, as the ARM3
performance results show, is not too small to be beneficial to
performance.

MIPS used 64KB caches for the R2000?  Because they could, in 1986.
Motorola used 16KB caches for the 88000?  Obviously 64KB is not all
that necessary.  Acorn used a 4KB shared cache for ARM3?  Because it
allowed them to do it on a single chip; it still gives good benefits.

My impression is that Bell was just grasping at straws to justify
their wrong choices.  He looked at other differences (rather than the
instruction set) between the MIPS R2000 and the VAX, and if it
represented something that was not available at acceptable cost in
1977 (in particular, 64KB caches), he used it as justification for the
VAX.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>