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Anton Ertl wrote:mitchalsup@aol.com (MitchAlsup1) writes:>
A pipelined machine in 1978 would have had 50% to 100% more circuit
boards than VAX 11/780, making it a lot more expensive.
What makes you think that a pipelined single-issue RV32GC would take
more circuit boards than VAX11/780? I have no data about discrete
implementations, but if we look at integrated ones and assume that the
number of transistors or the area corresponds to the number of circuit
boards in discrete implementations, the evidence goes in the opposite
direction:
The first article in this Mar-1987 HP Journal is about the
HP 9000 MODEL 840 and HP 3000 Series 930 implementing the HP PA ISA.
The cpu is 5 boards, 6 with FPU, built with standard and FAST TTL.
Implementation started in Apr-1983, prototype ready early 1984.
"[3 stage] pipeline fetches and executes an instruction every 125 ns,
a 4096-entry translation lookaside buffer (TLB) for high-speed address
translation, and 128K bytes of cache memory."
>
"The measured MIPS rate for the Model 840 varies from
about 3.5 to 8 MIPS with an average of 4.5 to 5."
>
which at 125 ns, 8 MHz clock is an IPC of 0.43 to 1.0, avg 0.625.
https://archive.org/download/Hewlett-Packard_Journal_Vol._38_No._3_1987-03_Hewlett-Packard/Hewlett-Packard_Journal_Vol._38_No._3_1987-03_Hewlett-Packard.pdf
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