Re: Why VAX Was the Ultimate CISC and Not RISC

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

In the current discussion we look at how RV32GC might have fared under
this constraint.

>
Sure. Except you need a much more complicated and resource-hungry compiler
than would have been reasonable to run on a VAX back then.

Looking at compiler technology available in 1975 close to DEC
[wulf+75] (highly recommended), I don't think so.  RISC-V code size
(as well as VAX code size) benefits from register allocation (existent
in that compiler, running on the PDP11).  Instruction scheduling would
have been helpful for performance, but would not help code size, and
is not particularly complex or resource-hungry when done on the
basic-block level (good enough for single-issue RISCs).

By contrast, making good use of the complex instructions of VAX in a
compiler consumed significant resources (e.g., Figure 2 of
https://dl.acm.org/doi/pdf/10.1145/502874.502876 reports about a
factor 1.5 more code in the code generator for VAX than for RISC-II).
Compilers at the time did not use the CISCy features much, which is
one reason why the IBM 801 project and later the Berkeley RISC and
Stanford MIPS proposed replacing them with a load/store architecture.
I think that a lot of that is inherent, but a part of it may be due to
the state of the art in instruction selection at the time.  So RISC
code comes easily out of compiler technology of the time, and for
smaller code, you just have to perform register allocation, which was
possible at the time, as demonstrated by Wulf et al.

@Book{wulf+75,
  author = {William Wulf and Richard K. Johnsson and Charles
                  B. Weinstock and Steven O. Hobbs and Charles M. Geschke},
  title = {The Design of an Optimizing Compiler},
  publisher = {Elsvier},
  year = {1975},
  isbn = {0-444-0164-6},
  annote = {Describes a complete Bliss/11 compiler for the
                  PDP-11.  It uses some interesting techniques: it
                  uses a (hand-constructed) tree parsing automaton for
                  parts of the code selection (Section~3.4); it
                  optimizes the use of unary complement operators
                  (Section~3.3); it uses a smart scheme to represent
                  a conservative approximation of the lifetime of
                  variables in constant space and uses that for
                  register allocation (Sections~4.1.3 and~4.3).}
}

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>