Re: Byte Addressability And Beyond

Michael S wrote:

On Sat, 4 May 2024 19:31:54 -0000 (UTC)
John Levine <johnl@taugh.com> wrote:

According to Lawrence D'Oliveiro  <ldo@nz.invalid>:

On Fri, 3 May 2024 22:11:44 -0500, BGB wrote:
 

Not a huge use-case in graphics, as noted, in most cases this is
done with 16 or 32 bit pixels; and bit-plane graphics are long
since dead. 

>
What happens if we go beyond 32 bits? For example, hardware might
support 10 bits per pixel component. 

 I dunno about you but I would align the elements on two-byte
boundaries and only store the high 10 of the 16 bits. It's not like
we're short of address space, and it's a lot quicker to multiply and
divide by 2 or 16 than by 10.
  

I agree about preferable solution and simplicity, but not about last
part.

Multiplication by 10 is only very slightly slower than multiplication
by 2 or 16 and the difference shouldn't be noticable by comparison with
other things that we want to do with pixel.

Multiplication by 10 used to index an array is not slower than a
multipication
by 16 (when the ISA is not brain dead)::
     LEA    Ri,[Ri,Ri<<3]
     LD     Rd,[Rp,Ri]
Compared to::
      SL     Ri,Ri,#4
     LD     Rd,[Rp,Ri]
{{Brain dead ISAs need not apply}}

On x386/AMD64 - multiplication by 2 is, depending on situation, zero or
1 instruction, multiplication by 16 is 1 instruction (lsh)  and
multiplication by 10 is either 1 instruction (IMUL) or two simpler
instructions (LEA+ADD).

Many times the ADD can be folded into a memory reference as illustrated
above.

On Arm and aarch64 it's approximately the same except that there are
situations in which multiplication by 16 is zero instructions.