Re: Why I've Dropped In

On Wed, 11 Jun 2025 22:00:33 +0000, EricP wrote:

MitchAlsup1 wrote:

On Wed, 11 Jun 2025 16:51:29 +0000, Anton Ertl wrote:
>

Program Counter: Some instruction sets (ARM A32, IIRC PDP-11 and VAX)
have the PC addressed like a GPR, although it clearly is a
special-purpose register.  Most RISCs don't have this, and don't even
have a PC-relative addressing mode or somesuch.  Instead, they use
ABIs where global pointers play a big role.

>
I consider IP as a GPR a mistake--I think the PDP-11 and VAX
people figured this out as Alpha did not repeat this mistake.
Maybe in a 16-bit machine it makes some sense but once you have
8-wide fetch-decode-execute it no longer does.

>
It had the advantage of meaningfully reusing some address modes
rather than having to add new opcode formats:
PC & autoincrement => immediate value (opcode data type gives size)
PC & autoincrement deferred => absolute address of data
PC & B/W/L relative => PC relative address of data
PC & B/W/L relative deferred => PC relative address of address of data

I can argue that there are other ways to encode each of the above
without using "address modes".

On the con side, for all PC-relative addressing the offset is
relative to the incremented PC after *each* operand specifier.
So two PC-rel references to the same location within a single
instruction will have different offsets.

This is exactly what made wide VAXs so hard to pipeline. At least
when I use IP as a means to access something in my ISA, the IP used
is the IP of the first word of the instruction {rather than a run-
ning copy of IP}

(Not a big deal but yet another thing one has to deal with in
Decode and carry with you in any uOps.)

It becomes quadratically harder as instruction width increases,
cubically if the accessed operands have variable widths.