Re: Concertlina II: Full Circle

On Sun, 23 Jun 2024 16:19:27 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:

While the vectorizing HW certainly has CRAY-like vector flip-flops
they are not addressable by SW. The code within the VEC--LOOP
brackets reads as if scalar:: So, My 66000 consumes exactly 2
OpCodes to provide an entire vector instruction set--one that
works as well as possible across various implementations.

Oh, yes, your VVM is wonderful.
My attempt at an imitation of VVM, at least, if not the real thing
that you have in your 66000, would be inferior in one important way to
Cray-style vector registers.
A virtual vector loop would take input vector values from memory, and
return results to memory. Yes, there are multiple operations within
the loop, but I am still assuming that the length and complexity of
such loops is constrained.
So if you have Cray-style vector registers, you have a place to store
intermediate results _between_ these loops that avoids referring to
memory.
In addition, one potentially catastrophic limitation is that, because
the meaning of register specifications in instructions is changed,
_there can't be any subroutine calls in such loops_. (Now that it's
typical for computers to have instructions that do log and trig
functions, this is slightly _less_ catastrophic, though.) Branches
within the loops and instruction predication, though, would still be
permitted.

John Savard