Re: Stacks, was Segments

On Tue, 11 Feb 2025 23:29:04 +0000, MitchAlsup1 wrote:

On Tue, 11 Feb 2025 20:49:24 +0000, Scott Lurndal wrote:
>

mitchalsup@aol.com (MitchAlsup1) writes:

>
This is basically how all modern CPUs handle it, yes.
>
But it is not relevent to the inbound traffic initiated
-by the device- which can't be translated by the CPU,
rather must be translated at some point between the
PCIe controller and the internal processor interconnect
(e.g. mesh).

>
I am tracing the path from user of device (core Guest OS).
If I don't understand this "should be simple" path, I am
too lost to continue from the device side looking towards
memory.
>
I can see how core can write Guest Physical Address into
device.BAR using config space access (with appropriate
MMU permissions).
>
But, right now: I can't see how the appropriate bit pattern
from core gets to HostBridge in MMI/O space and is recognized
by matching device.BAR down the PCIe tree.
>
core executes the following instruction::
>
       STH    R7,[Rdevice,#controlreg]
>
Rdevice has a Virtual Address bit pattern which after 1 level of
translation matches the bit pattern put into device.BAR at config.
>
#controlreg is the offset to the control reg.

Update:
I have figured out how to re-attach Guest Physical BAR back
as MMI/O commands enter the top of a PCIe tree.
Thanks to Scott Lurndal for being gentle with me.