Re: PCIe MSI-X interrupts

EricP wrote:

MitchAlsup1 wrote:

Sounds like SNARFing

Write-update depends on broadcasting all writes if that's what snarf
means.

General cache coherency policies broadcast a cores address to all
caches in the system, and if that cache contains that same cache
line, it responds with a SHARED back to requestor, or it invalidates
the line. We call this SNOOPing. It works well.
SNARF is a term whereby the owner of data broadcasts the data and
its address, and any cache containing that line will write the
data payload into its cache 9rather than invalidating and then
going back and fetching it anew. For certain kinds of data struct
SNARF is significantly more efficient than Invalidate-Refetch.
A single message around the system performs all the needed updates,
instead of 1 invalidate and K fetches.
SNARF is almost exclusively used as side-band signals hiding under
the cache coherent Interconnect command set.
SNARF is almost never available to software. It is more like micro-
Architecture talking to other microArchitecture.
Also note: µA-to-µA is rarely of line size and often uses physical
address bits not available through MMU tables.