Re: Stacks, was Segments

On Thu, 6 Feb 2025 16:41:45 +0000, EricP wrote:

MitchAlsup1 wrote:

On Wed, 5 Feb 2025 19:55:14 +0000, EricP wrote:
>

EricP wrote:

>
=====================================
For the present day we would want REW access control.
Naively this would require 4*3 = 12 bits in each PTE.
>
If apply the rules:
- we only need a meaningful subset of combinations: na, R, RE, RW, REW.
- no higher priv level can have less access than a lower priv level.
- we can save 1 combo because all 4 priv levels = na is redundant
  with the PTE Present bit being clear.
>
we can get this all down to a 4-bit PTE field:
>
Usr Sup Exc Krn
--- --- --- ---
na  na  na  R
na  na  na  RE
na  na  na  RW
na  na  na  REW
na  na  R   R
na  na  RE  RE
....
R   R   R   R
....
REW REW REW REW
>
The core's (thread's) privilege mode would enable access to the pages.
The PTE's access control field, which is derived from the kind of
mapped memory section, would not have to change between different
threads.

>
Or if you want the flexibility to choose your own REW combinations,
the 4-bit PTE access control field is an index to a 16 entry array
of 12-bit values for the four privilege levels.
>
That's better because then the OS can decide how it wants
the different memory sections and thread to behave and
removes the strict hardwired hierarchy of the prior rules.
>
The next problem though might be finding 4 bits in the PTE.

>
Another PTE bit I can find. Placing the 16×12 vector is more difficult,
even when I position it as 4 places of 16×3.

>
I don't understand what you said.
The 4-bit Access Control (AC) field is in the PTE.

Currently, PTE uses a 3-bit access control field, and PTE has
2-bits spare. So making access control larger is easy.

The 16 row x 12-bit AC-to-allowed-access programmable HW lookup table
is in the MMU.

How does 16×12 get to the MMU (or I/O MMU) ?? in such a way that super
cannot see things Hyper can see and the same with secure. So, somewhere
in the various control blocks I need to find space without changing
the overall use pattern of the control blocks and tables. Which is
why I alluded to 4×16×3 each interpretation of the 4-bit access control
is stored it its own natural place. It also means each layer can apply
its own interpretation (mapping).

The core's 2-bit mode selects-muxes one of the 3-bit allowed access
fields from the indexed 12-bits to extract the 3 R-E-W bits.

That much is straightforward.

The 2-bit mode comes from the LD/ST uOp, which was set to the mode
active when the instruction was decoded (so it can pipeline mode
changes).

Yes, core-state index follows the memref down the pipe.
Core-state index is written into MMI/O/device control block for the
DMA portion of a command, other CD indexes are associated with I/O
page faults and device errors.