Re: Computer architects leaving Intel...

On Wed, 18 Sep 2024 4:00:43 +0000, BGB wrote:

On 9/17/2024 6:04 PM, MitchAlsup1 wrote:

Still limited to 32-bit displacement from IP.
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How would you perform the following call::
current IP = 0x0000000000001234
target  IP = 0x7FFFFFFF00001234
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This is a single (2-word) instruction in my ISA, assuming GOT is
32-bit displaceable and 64-bit entries.
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Granted, but in plain RISC-V, there is no real better option.
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If one wants to generate 64-bit displacement, and doesn't want to load a
constant from memory:
   LUI X6, Disp20Hi       //20 bits
   ADDI X6, X6, Disp12Hi  //12 bits
   AUIPC X7, Disp20Lo
   ADD X7, Disp12Lo
   SLLI X6, X6, 32
   ADD X7, X7, X6

How very much simpler is::
     MEM    Rd,[IP,Ri<<s,DISP64]
1 instruction, 3 words, 1 decode cycle, no forwarding, shorter latency.

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Which is sort of the whole reason I am considering hacking around it
with an alternate encoding scheme.

Just put in real constants.

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New encoding scheme can in theory do:
   LEA X7, PC, Disp64
In a single 96-bit instruction.

Where is the indexing register?

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AUPIC is (and remains) a crutch (like LUI from MIPS)
a) it consumes an instruction (space and time)
b) it consumes a register unnecessarily
c) it consumes power that direct delivery of the constant would not

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Yeah, pretty much.
   LUI + AUIPC + JAL, eat nearly 27 bits of encoding space.
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