Re: Computer architects leaving Intel...

On Wed, 18 Sep 2024 17:55:34 +0000, BGB wrote:

On 9/18/2024 9:27 AM, MitchAlsup1 wrote:

On Wed, 18 Sep 2024 4:00:43 +0000, BGB wrote:
>

On 9/17/2024 6:04 PM, MitchAlsup1 wrote:

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Still limited to 32-bit displacement from IP.
>
How would you perform the following call::
current IP = 0x0000000000001234
target  IP = 0x7FFFFFFF00001234
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This is a single (2-word) instruction in my ISA, assuming GOT is
32-bit displaceable and 64-bit entries.
>

>
Granted, but in plain RISC-V, there is no real better option.
>
If one wants to generate 64-bit displacement, and doesn't want to load a
constant from memory:
   LUI X6, Disp20Hi       //20 bits
   ADDI X6, X6, Disp12Hi  //12 bits
   AUIPC X7, Disp20Lo
   ADD X7, Disp12Lo
   SLLI X6, X6, 32
   ADD X7, X7, X6

>
How very much simpler is::
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     MEM    Rd,[IP,Ri<<s,DISP64]
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1 instruction, 3 words, 1 decode cycle, no forwarding, shorter latency.

>
>
It is simpler, but N/E in RV64G...
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This is the whole issue of the idea:
   Remain backwards compatible with RV64G / RV64GC (in a binary sense).

So, you like sailing with an albatross tied around your neck:: Check.

*and* try to allow extending it in a way such that performance can be
less poor...

I should remind you that if you eliminate the compressed parts of
RISC-V you can fit the entire My 66000 ISA in the space remaining.
All the constants, all transcendentals, all the far-control transfers,
the efficient context switching, overhead free world switching,...
---------

>
Which is sort of the whole reason I am considering hacking around it
with an alternate encoding scheme.

>
Just put in real constants.

>
New encoding scheme can in theory do:
   LEA X7, PC, Disp64
In a single 96-bit instruction.

>
Where is the indexing register?

>
Generally the use of a displacement and index register are mutually
exclusive (and, cases that can make use of Disp AND Index are much less
common than Disp OR Index).

       COMMON ?alpha/ a(100,100), b(300,300),
..
       x = a(i,j)*b(j,i);
I see large displacements with indexing all the time from ASM out
of Brian's compiler.

I may still consider defining an encoding for this, but not yet. It is
in a similar boat as auto-increment. Both add resource cost with
relatively little benefit in terms of overall performance.
Auto-increment because if one has superscalar, the increment can usually
be co-executed. And, full [Rb+Ri*Sc+Disp], because it is just too
infrequent to really justify the extra cost of a 3-way adder even if
limited mostly to the low-order bits...

Myopathy--look it up.