Re: Chipsandcheese article on the CDC6600

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:

From what I read, the Model 91 was considered a technical (and
marketing) success, but commercially a failure (sold at a loss, and
therefore quickly canceled).  But apparently the market benefit was
enough that they then built the 360/195 and 370/195.  15 91s were
built and about 20 195s.  The 195 was withdrawn in 1977, and AFAIK
that was the end of IBM's supercomputing ambitions for a while.  This
may have had to do with the introduction of the Cray-1 in 1976 or the
IBM 3033 in 1977.  IBM eventually announced the optional vector
facility for the 3090 in 1985.  OoO processing vanished from S/360
successors with the 195 and only reappeared quite a while after it had
appeared in Intel and RISC CPUs.

... also shortly after joining IBM, was asked if I could help with
project to multi-thread 370/195 .... also from acs end page:
https://people.computing.clemson.edu/~mark/acs_end.html Sidebar:
Multithreading

In summer 1968, Ed Sussenguth investigated making the ACS/360 into a
multithreaded design by adding a second instruction counter and a second
set of registers to the simulator. Instructions were tagged with an
additional "red/blue" bit to designate the instruction stream and
register set; and, as was expected, the utilization of the functional
units increased since more independent instructions were available.

IBM patents and disclosures on multithreading include:

US Patent 3,728,692, J.W. Fennel, Jr., "Instruction selection in a
two-program counter instruction unit," filed August 1971, and issued
April 1973.

US Patent 3,771,138, J.O. Celtruda, et al., "Apparatus and method for
serializing instructions from two independent instruction streams,"
filed August 1971, and issued November 1973. [Note that John Earle is
one of the inventors listed on the '138.]

"Multiple instruction stream uniprocessor," IBM Technical Disclosure
 Bulletin, January 1976, 2pp. [for S/370]

... snip ...

370/195 had 64 instruction pipeline and could do out-of-order ... but
didn't have branch prediction or speculative executive ... so
conditional branches drained pipeline and most codes ran at half 195
rated throubhput. Simulating multiprocessor with red/blue instruction
streams ... could get two half-rate streams running 195 a full speed
(modulo MVT/MVS two processor support only having 1.2-1.5 throughput of
single processor). The whole thing was shutdown when it was decided to
add virtual memory to all 370s ... which was decided not practical for
195.

z195 (july2010) documents claim that half of the per-processor
improvement in mip rate (compared to the previous z10) is due to
introduction of introduction of things like out-of-order.
   
--
virtualization experience starting Jan1968, online at home since Mar1970