Re: Tonights Tradeoff

On Thu, 12 Sep 2024 19:28:19 +0000, Robert Finch wrote:

On 2024-09-12 12:46 p.m., MitchAlsup1 wrote:

On Thu, 12 Sep 2024 3:37:22 +0000, Robert Finch wrote:
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On 2024-09-11 11:48 a.m., Stephen Fuld wrote:

On 9/11/2024 6:54 AM, Robert Finch wrote:
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I have found that there can be a lot of registers available if they
are implemented in BRAMs. BRAMs have lots of depth compared to LUT
RAMs. BRAMs have a one cycle latency but that is just part of the
pipeline. In Q+ about 40k LUTs are being used just to keep track of
registers. (rename mappings and checkpoints).
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Given a lot of available registers I keep considering trying a VLIW
design similar to the Itanium, rotating register and all. But I have a
lot invested in OoO.
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Q+ has seven in-order pipeline stages before things get to the re-
order buffer.

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Does each of these take a clock cycle?  If so, that seems excessive.
What is your cost for a mis-predicted branch?
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Each stage takes one clock cycle. Unconditional branches are detected at
the second stage and taken then so they do not consume as many clocks.
There are two extra stages to handle vector instructions. Those two
stages could be removed if vectors are not needed.
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Mis-predicted branches are really expensive. They take about six clocks,
plus the seven clocks to refill the pipeline, so it is about 13 clocks.
Seems like it should be possible to reduce the number of clocks of
processing during the miss, but I have not got around to it yet. There
is a branch miss state machine that restores the checkpoint. Branches
need a lot of work yet.

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In a machine I did in 1990-2 we would fetch down the alternate path
and put the recovery instructions in a buffer, so when a branch was
mispredicted, the instructions were already present.
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So, you can't help the 6 cycles of branch verification latency,
but you can fix the pipeline refill latency.
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We got 2.05 i/c on XLISP SPECnit 89 mostly because of the low backup
overhead.
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That sounds like a good idea. The fetch typically idles for a few cycles
as it can fetch more instructions than can be consumed in a single
cycle. So, while it’s idling it could be fetching down an alternate
path. Part of the pipeline would need to be replicated doubling up on
the size. Then an A/B switch happens which selects the right pipeline.

You want the alternate path buffer to be staged up ready to go. You
do not necessarily have to dedicate any post decode pipeline stages to
them. You can fetch these from the buffer indexed by branch number,
so when the branch fires to execute the verify stuff, you are fetching
the backup instructions.
You CAN use the renamer state after the previously issued group so the
buffer contains already renamed registers--If you back up and use these
instructions you threw away the post issue parts of the renamer anyway.
This enables you to take a cycle to back up the renamer without penalty.

Would not want to queue to the reorder buffer from the alternate path,
as there is a bit of a bottleneck at queue. Not wondering what to do
about multiple branches. Multiple pipelines and more switches? Front-end
would look like a pipeline tree to handle multiple outstanding branches.
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Was wondering what to do with the extra fetch bandwidth. Fetching two
cache-lines at once means there may have been up to 21 instructions
fetched. But its only a four-wide machine.

For my 6-wide machine I am fetching 1/2 a cache line twice for the
sequential path and 1/2 a cache line for the alternate path from
an 8 banked ICache.

                                           I was going to try and feed
multiple cores from the same cache. Core A is performance, core B is
average, and core C is economy using left-over bandwidth from A and B.

ARM's big little strategy, with some power philosophy, gives you that
average as a little core running at high voltage and frequency.

I can code the alternate path fetch up and try it in SIM, but it is too
large for my FPGA right now. Another config option. Might put the switch
before the rename stage. Nothing like squeezing a mega-LUT design into
100k LUTs. Getting a feel for the size of things. A two-wide in-order
core would easily fit. Even a simple two-wide out-of-order core would
likely fit, if one stuck to 32-bits and a RISC instruction set. A
four-wide OoO core with lots of features is pushing it.