Re: MM instruction and the pipeline

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Sujet : Re: MM instruction and the pipeline
De : mitchalsup (at) *nospam* aol.com (MitchAlsup1)
Groupes : comp.arch
Date : 16. Oct 2024, 20:26:46
Autres entêtes
Organisation : Rocksolid Light
Message-ID : <a0b104f75864e253618d80c2c5726ea6@www.novabbs.org>
References : 1
User-Agent : Rocksolid Light
On Wed, 16 Oct 2024 5:56:34 +0000, Stephen Fuld wrote:

Even though this is about the MM instruction, and the MM instruction is
mentioned in other threads, they have lots of other stuff (thread
drift), and this isn't related to C, standard or otherwise, so I thought
it best to start a new thread,
>
My questions are about what happens to subsequent instructions that
immediately follow the MM in the stream when an MM instruction is
executing.  Since an MM instruction may take quite a long time (in
computer time) to complete I think it is useful to know what else can
happen while the MM is executing.
>
I will phrase this as a series of questions.
>
1. I assume that subsequent non-memory reference instructions can
proceed simultaneously with the MM.  Is that correct?
Yes, they may begin but they cannot retire.

2. Can a load or store where the memory address is in neither the source
nor the destination of the MM proceed simultaneously with the MM
Yes, in higher end implementations--after checking for no-conflict
{and this is dependent on accessing DRAM not MMI/O or config spaces}

3. Can a load where the memory address is within the source of the MM
proceed?
It is just read data, so, yes--at least theoretically.

For the next questions, assume for exposition that the MM has proceeded
to complete 1/3 of the move when the following instructions come up.
>
4. Can a load in the first third of the destination range proceed?
>
5. Can a store in the first third of the source range proceed?
>
6. Can a store in the first third of the destination range proceed?
In all 3 of these cases; one much have a good way to determine what has
already been MMed and what is waiting to be MMed. A low end
implementation
is unlikely to have such, a high end will have such.
On the other hand, MM is basically going to saturate the cache ports
(if for no other reason than being as fast as it can be) so, there
may not be a lot of AGEN capability or cache access port availability.
So, the faster one makes MM (and by extension MS) the less one needs
of overlap and pipelining.
>
>

Date Sujet#  Auteur
16 Oct 24 * MM instruction and the pipeline13Stephen Fuld
16 Oct 24 +* Re: MM instruction and the pipeline3MitchAlsup1
17 Oct 24 i`* Re: MM instruction and the pipeline2Stephen Fuld
17 Oct 24 i `- Re: MM instruction and the pipeline1MitchAlsup1
16 Oct 24 `* Re: MM instruction and the pipeline9Paul A. Clayton
16 Oct 24  `* Re: MM instruction and the pipeline8MitchAlsup1
20 Oct 24   `* Re: MM instruction and the pipeline7Paul A. Clayton
21 Oct 24    +* Re: MM instruction and the pipeline3MitchAlsup1
21 Oct 24    i+- Re: MM instruction and the pipeline1Stephen Fuld
22 Oct 24    i`- Re: MM instruction and the pipeline1MitchAlsup1
21 Oct 24    `* Re: MM instruction and the pipeline3Anton Ertl
21 Oct 24     `* Re: MM instruction and the pipeline2Michael S
22 Oct 24      `- Re: MM instruction and the pipeline1MitchAlsup1

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