Re: Privilege Levels Below User

I forgot to add that Mc 88120 had these features in 1992.
There was a staging buffer between AGEN and LDalign where up to 48
memory reference instructions could wait for data to become available,
for modified results to wait to be written back to DCache, for inst-
ructions to wait for memory order to resolve, and it could even retarget when modified data could go. we called this thing the
Conditional Cache.
Stores waited for retirement.
Mises waited for retirement to modify DCache
Memory references could access data in CC so it added no0 cycle latency
and acted like memory forwarding (==register forwarding)
but the DCache was not modified until the causing instruction
to retire. The CC was in effect the memory pipeline !!
..
For example one could have modified data waiting for a DCache
write to become available when a subsequent memory reference displaces the first line out towards memory, so there is no
line in the cache to write to !! so the CC wrote the data out
towards memory. 1992 !! And it could run MATRIX 300 at 5.9 IPC.