Re: Misc: BGBCC targeting RV64G, initial results...

On Fri, 27 Sep 2024 9:46:01 +0000, BGB wrote:

Had recently been working on getting BGBCC to target RV64G.
>
Array Load/Store:

     M66: 1 instruction

   XG2: 1 instruction
   RV64: 3 instructions
>
Global Variable:

     M66: 1 instruction (anywhere in 64-bit memory)

   XG2: 1 instruction (if within 2K of GBR)
   RV64: 1 or 4 instructions
>
Constant Load into register (not R5):

     M66: 0 instructions

   XG2: 1 instruction
   RV64: ~ 1-6
>
Operator with 32-bit immediate:

     M66:  1 instruction

   BJX2: 1 instruction;
   RV64: 3 instructions.
>
Operator with 64-bit immediate:

     M66:  1 instruction

   BJX2: 1 instruction;
   RV64: 4-9 instructions.
>
>
>
Floating point is still a bit of a hack, as it is currently implemented
by shuffling values between GPRs and FPRs, but sorta works.

My 66000 has a common register file.

>
RV's selection of 3R compare ops is more limited:
   RV: SLT, SLTU
   BJX2: CMPEQ, CMPNE, CMPGT, CMPGE, CMPHI, CMPHS, TST, NTST
A lot of these cases require a multi-op sequence to implement with just
SLT and SLTU.

My 55000 can do::  1 < i && i <= MAX in 1 instruction

>
....