Re: number of registers

On Wed, 21 Aug 2024 12:00:47 +0000, Anton Ertl wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

On Tue, 20 Aug 2024 18:18:25 +0000, EricP wrote:

On OoO, if the reservation stations are valueless, you need a real
physical register to stash the temp value as there is no guarantee
the OP part of the uOp will launch just when the LD part finishes
doing its thing and forwards the value.

>
In the LD-OP-ST microarchitecture there would be some buffer
that carries the intermediate values through the execution
window. And, Yes, you can build a LD-OP-ST reservation station
(Athlon and Opteron did).

>
All the material I have seen is that AMD has a load-store ROP, but the
op in between is in a separate functional unit, with a separate
scheduler entry; and I expect that the load-store ROP occupies the
load/store scheduler(s) twice: once for the load part, once for the
store part.

The LD-OP-STs in Athlon and Opteron had a memory OpCode and calculation
OpCode, and was performed in such a way that the physical address of
the LD was used for the ST when its time came. The calculation OpCode
was an ALU or the IMUL/DIV unit.

             There is also something about macroops that can be
load-op-stores, but from what I have read, when it comes to execution,
they are split into ROPs.
>
If you have more details that contradict the information published up
to now, please let us know more about them.
>
On the Intel side, LD-OP-ST is split into three uops according to
everything I have read.  Apparently they are satisfied with this
approach, or they would have gone for something else.
>
- anton