Re: Interview with Power's chief designer

On Fri, 27 Dec 2024 13:29:22 +0000, Thomas Koenig wrote:

Not sure how many of you read Chips and Cheese, but in case you're
interested: Here is an inteview with IBM Power's chief designer,
Bill Starke:
>
https://old.chipsandcheese.com/2024/12/26/ibm-power-whats-next/
>
There is a lot of talk on OMI (he really doesn't like DDR, and gives
reasons, especially the amount of memory and reliability), plus some
detail on POWER11, which apparently will be a microarchitectural
evolution, but no new ISA parts, and the philosophy behind the
chiplet design they are about to do for the next generation after
that.

He makes a compelling point that DDR is using too many pins and
still does not provide the desired BW available for that number
pf pins. And that a SEREDS interface to DRAMs provide easier to
achieve signaling and larger memories at the same time--similar
to what CXL:memory is attempting.

Apparently, nobody knows what its name will be, but it might
be something like "Power 11 plus one".

Let me take a guess::
{I have to state that I have heard and read nothing}