Re: Why I've Dropped In

On Wed, 11 Jun 2025 16:51:29 +0000, Anton Ertl wrote:

BGB <cr88192@gmail.com> writes:

For example, SPRs can be, by definition,
not the same as GPRs. Say, if you have an SP or LR, almost by
definition, you will not be using it as a GPR.
>
So, if ZR/LR/SP/GP are "not GPR", this is fine.

>
I assume you mean Zero register, link register, stack pointer, global
pointer.  On most register architectures (those with GPRs) all of them
are addressed as GPRs in most instructions.  Specifically:
>
Zero register: The CISCs (S/360, PDP-11, VAX, IA-32, AMD64) don't have
a zero register, but use immediate 0 instead.  Most RISCs have a
register (register 0 or 31) that is addressed like a GPR, but really
is a special-purpose register: It reads as 0 and writing to it has no
effect.  Power has some instructions that treat register 0 as zero
register and others that treat it as GPR.

My 66000 is a RISC architecture that does NOT have a zero register.
Most instructions have the ability to use the 5-bit register
specifier as a 5-bit immediate, and for these instructions; #0
signifies zero in both integer and floating point senses. #1
signifies 0x0000000000000001 or 0x7FE0000000000000, ... so that
one can do FADD R7,R19,#7 as a single 32-bit instruction word,
saving instructions and code space. {Brian gets credit for this}
Over on the memory side:: Rbase  = 0 implies IP is the Base register
                          Rindex = 0 implies no indexing (but still
having
access to DISP32 and DISP64 constants)
Over on the call/return side: When safe stack is in use, RETaddr
goes on the top of CSP and R0 is not modified, but when safe stack
is not in use, R0 <= RETaddr. The RET instruction, then, does the
right thing based on the status of the Safe-Stack in use flag.
CSP (call stack pointer) is used to hold RETaddr and preserved
registers in a way the called program can neither read nor write
adding safety against actual attacks, and bad programming.
And then there is the CALX instruction--which is a LDD IP,[address]--
which transfers control through a table in memory to an entry point
in the table. Good for external linkage and method calls. An
interesting point, here, is that this is only for CALL/RET and not
for branching--thus, it can be predicted better than with typical
jump-predict-tables because you are not predicting at time of JMP
but you are predicting at the time of the LDD; so, you can use
LOBs of the address to help with the prediction.

Link register: On some architectures there is a register that is a GPR
as far as most instructions are concerned.  But the call instruction
with immediate (relative) target uses that register as implicit target
for the return address.  MIPS is an example of that.  Power has LR as
a special-purpose register.

You could call my use of safe-stack as putting LR in a "more-better"
place than in a GPR.

Stack pointer: That's just software-defined on many register
architectures, i.e., one could change the ABI to use a different stack
pointer, and the resulting code would have the same size and speed.
An interesting case is RISC-V.  In RV64G it's just software-defined,
but the C (compressed) extension defines some instructions that
provide smaller instructions for a specific assignment of SP to the
GPRs; I expect that similar things happen for other compressed
instruction set extensions.

My 66000 did something similar:: The ENTER and EXIT instructions
use SP == R31 (or CSP) implicitly, values needing preserved are
placed in memory the callee cannot LD not ST. Other than ENTER
EXIT, and RET, SP could be any register.
Interesting point:: the compiled code is not sensitive to the
setting of the safe-stack flag--only the thread control regs.
The only pieces of SW that need cognition of safe-stack are
longjump() and stack-walk-back as used by TRY-THROW-CATCH.
Both use the EXIT instruction in a "special" way to peal back
layers on the stack.

Global pointer: That's just software-defined on all register
architectures I am aware of.

In My 66000, it is simply an address constant. There is no rational
to consume a register to get at something one can access with a
longer address constant.

Program Counter: Some instruction sets (ARM A32, IIRC PDP-11 and VAX)
have the PC addressed like a GPR, although it clearly is a
special-purpose register.  Most RISCs don't have this, and don't even
have a PC-relative addressing mode or somesuch.  Instead, they use
ABIs where global pointers play a big role.

I consider IP as a GPR a mistake--I think the PDP-11 and VAX
people figured this out as Alpha did not repeat this mistake.
Maybe in a 16-bit machine it makes some sense but once you have
8-wide fetch-decode-execute it no longer does.

- anton