Re: Chipsandcheese article on the CDC6600

On Mon, 22 Jul 2024 12:52:35 +0000, Anton Ertl wrote:

Michael S <already5chosen@yahoo.com> writes:

At the end, the influence of 6600 on computers we use today is close to
zero. On the other hand, influence of S/360 Model 85 is massive and
influence of S/360 Model 91 is significant, although far less than the
credit it is often given in popular articles.

>
Yes, all modern computers have virtual memory (which started with
Atlas (and later S/360 Model 67), they have caches, which started with
Titan (and later S/360 Model 85), they have reservation stations
(which started with S/360 Model 91).
>
However, the main reason why reservation stations won is because
hardware branch prediction outpaced compiler branch prediction since
the early 1990s*, and because the reorder buffer was invented, neither
of which is due to anything done in any S/360 model or the CDC 6600).
>
If hardware branch prediction had never been invented or had turned
out to be a dud, maybe we would all be using EPIC architectures that
use scoreboards rather then reservation stations; or maybe the

CDC 7600 predicted backwards branches to be taken and that this was
worth a handful of % in performance gain:: and used no storage to
do it. So an "as dumb as possible" predictor delivered gains.
It is all uphill from there.

register interlocks that were used in advanced in-order RISCs (those
that Mitch Alsup calls OoO) and AFAIK in IA-64 implementations were
good enough and one would have done without scoreboard.

Register interlocks is the means to allow GHW to move instructions
around in the pipeline--you just have to obey RAW, WAR, and WAW
hazards.

>
[*] More supercomputing-oriented people may claim that it has to do
with the number of in-flight memory accesses, but actually IA-64 shone
on SPEC FP (where in-flight memory accesses are more important than
for SPECint), so it seems that there are ways to get the needed
in-flight memory accesses with in-order execution.

IA-64 had 2× the number of pins compared to its x86 brethren.
No wonder it could consume more BW.