Re: Stealing a Great Idea from the 6600

While I much admire CDC 6600 PPs and how much work those puppies did
allowing the big number crunchers to <well> crunch numbers::
With modern technology allowing 32-128 CPUs on a single die--there is
no reason to limit the width of a PP to 12-bits (1965:: yes there was
ample reason:: 2024 no reason whatsoever.) There is little reason to
even do 32-bit PPs when it cost so little more to get a 64-bit core.
In 2005-6 I was looking into a Verilog full x86-64 core {less FP} so
that those smaller CPUs could run ISRs and kernel codes to offload the
big CPUs from I/O duties. Done in Verilog meant anyone could compile it
onto another die so the I/O CPUs were out on the PCIe tree nanoseconds
away from the peripherals rather than microseconds away. Close enough
to perform the DMA activities on behalf of the devices; and consuming
interrupts so the bigger cores did not see any of them (except timer).
As Scott stated:: there does not seem to be any reason to need FP on a
core only doing I/O and kernel queueing services.