Re: Reverse engineering of Intel branch predictors

In MY 66000 ISA::
a) RET is not predicted
b) switch() is not predicted
c) method calls are not predicted
d) GOT calls are not predicted
>
Which pretty much gets rid of the problem.

By "the problem" I guess you mean "indirect jumps", right?

c+d) GOT calls and method calls use the CALX instruction which
loads IP from memory--thus not needing prediction--and not using
a trampoline, either.

I don't understand the "thus not needing prediction".  Loading IP from
memory takes time, doesn't it?  Depending on your memory hierarchy and
where the data is held, I'd say a minimum of 3 cycles and often more.
What do you do during those cycles?

b) switch() is the JTT instruction

IIUC this is basically like CALX, except with a bit more work to
generate the address from which you fetch the IP (plus a bit more work
to generate the IP from the fetched data as well).  So: same question.


        Stefan