Re: Efficiency of in-order vs. OoO

Anton Ertl wrote:

scott@slp53.sl.home (Scott Lurndal) writes:

There is a significant demand for performance monitoring.   Note
that in addition to to standard performance monitoring registers,
AArch64 also (optionally) supports statistical profiling and
out-of-band instruction tracing (ETF).   The demand from users
is such that all those features are present in most designs.

 Interesting.  I would have expected that the likes of me are few and
far between, and easy to ignore for a big company like ARM, Intel or AMD.
 My theory was that the CPU manufacturers put performance monitoring
counters in CPUs in order to understand the performance of real-world
programs themselves, and how they should tweak the successor core to
relieve it of bottlenecks.

Having reverse engineered the original Pentium EMON counters I got a meeting with Intel about their next cpu (the PentiumPro), what I was told about the Pentium was that this chip was the first one which was too complicated to create/sell an In-Circuit Emulator (ICE) version, so instead they added a bunch of counters for near-zero overhead monitoring and depended on a bit-serial read-out when they needed to dump all state for debugging. (I have forgotten the proper term for that interface! :-( )
Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"