Re: Stealing a Great Idea from the 6600

MitchAlsup1 wrote:

BGB wrote:
 

On 4/20/2024 5:03 PM, MitchAlsup1 wrote:
Like, in-order superscalar isn't going to do crap if nearly every instruction depends on every preceding instruction. Even pipelining can't help much with this.

 Pipelining CREATED this (back to back dependencies). No amount of
pipelining can eradicate RAW data dependencies.
 

The compiler can shuffle the instructions into an order to limit the number of register dependencies and better fit the pipeline. But, then, most of the "hard parts" are already done (so it doesn't take much more for the compiler to flag which instructions can run in parallel).

 Compiler scheduling works for exactly 1 pipeline implementation and
is suboptimal for all others.

Well, yeah.
OTOH, if your (definitely not my!) compiler can schedule a 4-wide static ordering of operations, then it will be very nearly optimal on 2-wide and 3-wide as well. (The difference is typically in a bit more loop setup and cleanup code than needed.)
Hand-optimizing Pentium asm code did teach me to "think like a cpu", which is probably the only part of the experience which is still kind of relevant. :-)
Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"